Difference between RISC and CISC

RISC-Means Reduced Instruction Set Computer.a Risc  system has reduced number of instructions and more
importantly it is load store architecture were  pipelining can be implemented easily.

Eg.ATMEL AVR

CISC-Means Complex instruction set architecure.A CISC   system has complex instructions such as direct
addition between data in two memory locations.

Eg.8085 

CISC
 

Pronounced sisk, and stands for Complex Instruction Set Computer. Most PC's use CPU based on this architecture. For instance Intel and AMD CPU's are based on CISC architectures.
 

Typically CISC chips have a large amount of different and complex instructions. The philosophy behind it is that hardware is always faster than software, therefore one should make a powerful instructionset, which provides programmers with assembly instructions to do a lot with short programs.
 

In common CISC chips are relatively slow (compared to RISC chips) per instruction, but use little (less than RISC) instructions.
 

RISC
 

Pronounced risk, and stands for Reduced Instruction Set Computer. RISC chips evolved around the mid-1980 as a reaction at CISC chips. The philosophy behind it is that almost no one uses complex assembly language instructions as used by CISC, and people mostly use compilers which never use complex instructions. Apple for instance uses RISC chips.
 

Therefore fewer, simpler and faster instructions would be better, than the large, complex and slower CISC instructions. However, more instructions are needed to accomplish a task.
An other advantage of RISC is that - in theory - because of the more simple instructions, RISC chips require fewer transistors, which makes them easier to design and cheaper to produce.
Finally, it's easier to write powerful optimised compilers, since fewer instructions exist.

 

RISC  vs  CISC
 

There is still considerable controversy among experts about which architecture is better. Some say that RISC is cheaper and faster and therefor the architecture of the future.
 

Others note that by making the hardware simpler, RISC puts a greater burden on the software. Software needs to become more complex. Software developers need to write more lines for the same tasks.
 

Therefore they argue that RISC is not the architecture of the future, since conventional CISC chips are becoming faster and cheaper anyway.
 

RISC has now existed more than 10 years and hasn't been able to kick CISC out of the market. If we forget about the embedded market and mainly look at the market for PC's, workstations and servers I guess a least 75% of the processors are based on the CISC architecture. Most of them the x86 standard (Intel, AMD, etc.), but even in the mainframe territory CISC is dominant via the IBM/390 chip. Looks like CISC is here to stay …
 

Is RISC than really not better? The answer isn't quite that simple. RISC and CISC architectures are becoming more and more alike. Many of today's RISC chips support just as many instructions as yesterday's CISC chips. The PowerPC 601, for example, supports more instructions than the Pentium. Yet the 601 is considered a RISC chip, while the Pentium is definitely CISC. Further more today's CISC chips use many techniques formerly associated with RISC chips.

CISC

• Instruction Set:large set of instruction with variable size (16 to 64)
• Addressing Modes: 12-24
• General Purpose registers: 8-24
• Clock rate: 33-50MHz in 1992

RISC

• Instruction Set:Small set of instruction with fixed size (32-bit)
• Addressing Modes: 3-5
• General Purpose registers: 32-192
• Clock rate: 50-150MHz in 1993

Von Neumann and Harvard architecture

von Neumann architecture: computers has a single, common memory space in which both program instructions and data are stored. There is a single internal data bus that fetches both instructions and data. They can not be performed at the same time.

Harvard architecture: computers have separate memory areas for program instructions and data. There are two or more internal data buses, which allow simultaneous access to both instructions and data. The CPU fetches program instructions on the program memory bus.

The 8051 microcontrollers (MCS-51) have an 8-bit data bus. They can address 64K of external data memory and 64K of external program memory. These may be separate blocks of memory, so that up to 128K of memory can be attached to the microcontroller. Separate blocks of code and data memory are referred to as the Harvard architecture. A single block of memory may be mapped to act as both data and program memory. This is referred to as the Von Neumann architecture.

The 8051 has two separate read signals, RD# (P3.7) and PSEN#. The RD# (P3.7) is activated by clearing to logic level 0 when a byte is to be read from external data memory, PSEN#, from external program memory. All external code is fetched from external program memory. The bytes from external program memory may be read by special read instructions such as the MOVC. And there are separate instructions to read from external data memory, such as the MOVX instruction. In order to read from the same block using either the RD# signal or the PSEN# signal, the two signals are combined with a logic AND operation. This way, the output of the AND gate is low when either input is low.

By adopting the Von Neumann architecture, code may be written to memory as data bytes, and then executed as program instructions.